As is well known, the build-up of static charge may lead to extremely high voltage developed near an integrated circuit (IC). Electrostatic discharge (ESD) refers to the phenomenon of the electrical discharge of high current for short duration resulting from the build up of static charge on a particular IC package, or on a nearby human handling that particular IC package. ESD is a serious problem for semiconductor devices since it has the potential to destroy an entire IC. Since ESD events occur often across the silicon circuits attached to the package terminals, circuit designers have concentrated their efforts on developing adequate protection mechanisms for these sensitive circuits.
Ideally an ESD protection circuit should be able to protect an IC against any conceivable static discharge by non-destructively passing large currents through a low impedance path in a short time.
One technique to protect the components (e.g., transistors, inactive devices, etc.) of an integrated circuit from an electrostatic discharge (ESD) event is to add circuitry intended to sink or remove the charge associated with the ESD event. For example, a wide clamping device (e.g., a transistor having a width significant to allow the charge to draw away without creating a damaging current density) may be placed in parallel or in series with the portion of the integrated circuit to be protected. Due to the width of the clamping device, it may sink the charge associated with the ESD device and alleviate high voltage levels that may otherwise result.
However, as manufacturing techniques improve, the channel length of transistors is typically reduced and gate oxides thinned, which, in turn, may increase the leakage of the transistors. Consequently, the clamping devices may become a significant source of leakage current while the integrated circuit is in operation. Thus, there is a continuing need for better ways to provide charge protection to an integrated circuit that has reduced leakage currents.